1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a method and circuitry for providing a differential reset stabilized latch having offset cancellation.
2. Discussion of the Prior Art
Referring to FIG. 1A, in the operation of a conventional differential reset stabilized latch, negative feedback is first applied around the latch amplifier for reset stabilization. In the ideal case, V.sub.A =V.sub.B. Then, as shown in FIG. 1B, the negative feedback is removed and the input switches are thrown to reverse the differential latch inputs, V.sub.signal and V.sub.ref. For purposes of this discussion and the detailed description that follows, it is assumed that V.sub.signal is greater than V.sub.ref ; however, the concepts presented herein are equally valid if V.sub.signal is less than V.sub.ref. The voltage on the latch amplifier after the input switches are thrown is as shown in FIG. 1B, where the V.sub.signal is the differential signal and G is the gain. As shown in FIG. 1C, latch input V.sub.signal is then latched in by applying positive feedback around the latch amplifier. Thus, the latch, in this ideal case, is now in the high state corresponding to the assumption that latch input V.sub.signal is greater than latch reference V.sub.ref. This ideal latch will latch high even if V.sub.signal is only infinitesimally greater than V.sub.ref.
Unfortunately, the two input transistors of a differential reset stabilized latch are never perfectly matched. As a result, a differential offset voltage is inherent at the input to such devices. That is, referring back to FIG. 1A, V.sub.A does not equal V.sub.B after application of negative feedback.
Referring again to FIG. 1B, as just stated, for a "real world" differential reset stabilized latch, V.sub.A will be different from V.sub.B. The offset voltage V.sub.os can be calculated by determining what change in V.sub.A is required to make the voltage at Node A equal to the voltage at Node C. ##EQU1## Assuming V.sub.os is positive, if the differential signal .DELTA.V.sub.signal is less than V.sub.os, then the latch will provide the wrong output when positive feedback is applied. Thus, the "real world" latch requires that V.sub.signal be greater than V.sub.ref by at least the offset voltage V.sub.os before it will latch high.